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VLSI Design

VLSI Syllabus

1. Introduction to VLSI

  • Evolution of VLSI Systems
  • Applications of VLSI Systems
  • Processor Based Systems
  • FPGA Based Systems
  • Digital System Design Using FPGAs
  • Introduction to HDL languages

2. Digital Electronics

  • Introduction to Digital Electronics
  • Number systems
  • Code conversions
  • Arithmetic’s
  • Boolean algebra
  • Logic gates

 3. Combinational logic design

  • Standard representation of logical functions
  • Karnaugh map method
  • MSI circuits
  • Multiplexers/demultiplexers
  • Adders / subtractors
  • Arithmetic Logic Unit (ALU)
  • Encoders/ Decoders

4. Flip Flops

  • Flip-flops
  • Type of Flip flops
  • Conversion of flip flops
  • Application of flip flops

5. Sequentional circuit design

  • Registers
  • Types of shift registers
  • Application of registers
  • Counters
  • Ripple or Asynchronous counters
  • Synchronous counters
  • Clocked sequential circuits

6. Designing of Memories

  • Introduction
  • Memory Organization and operation
  • Expanding memory size
  • Expanding memory capacity
  • Different types of memories

7.  Programmable Logic devices

  • Introduction
  • Programmable logic array (PLAs)
  • Programmable array logic (PALs)
  • Complex programmable logic devices (CPLDs)
  • Field programmable gate array (FPGA)
  • Computer-Aided Design Tools (CAD)

Design and synthesis by using Verilog HDL:

Introduction to Verilog HDL

  • Typical Design flow
  • Importance of HDL’s
  • Popularity of Verilog HDL

Modeling Concepts

  • Design methodologies
  • Module concept
  • types of modeling

Basic Concepts

  • Lexical Conventions
  • Number Specifications
  • Strings
  • Data Types
  • System Task
  • Compiler Directives

Modules

  • List of Ports
  • Port Declaration
  • Port Connection Pins

Gate Level Modeling

  • Different Types of Gates
  • Gate Delays

Data Flow modeling

  • Continuous Assignments
  • Delays
  • Expression Operators
  • Operators Types

Behavioral Modeling

  • Structured Procedures
  • Initial Statement
  • Always Statement
  • Event- Base Timing Control
  • Conditional Statements
  • If Statements
  • Case Statements
  • Loop Statements

Structural Modeling

  • component instantiation
  • Interfacing of sub modules

FSM Modeling

  • Types of FSMs
  • Moore FSM
  • Melay FSM
  • Controller Development
  • Sequence Detectors

Memory Modeling

  • RAM
  • ROM
  • LUT

Task and Functions

  • Different between Task and Function
  • Function
  • Task

Switch Level modeling (optional)

  • nmos
  • pmos
  • cmos
  • combinational circuit design with cmos
  • Sequential circuit design with cmos

Test Bench

  • Modeling a Test Bench
  • Test Bench for Combinational Circuits
  • Test Bench for Sequential Circuits
  • Test Bench for Memories Circuits
  • Test Bench for Controllers

Design and synthesis by using VHDL:

Introduction to VHDL

  • Introduction to VHDL
  • Code structure
  • Library Functions
  • Entity
  • Architecture
  • Configuration Declaration
  • Package Declaration

Elements of VHDL LANGUAGES

  • Different Data types
  • Operators
  • Attributes
  • Generic
  • Identifiers
  • Variables & Signals

Different types of VHDL Modeling

  • Behavioral modeling
  • Modeling techniques
  • If statement
  • Case statement
  • Wait statement
  • Loop statement
  • Process statement

Dataflow modeling

  • When statements.
  • Block statement
  • Generate statement

Structural Modeling

  • Component declaration
  • Component instantiation

FSM Modeling

  • Types of FSMs
  • Moore FSM
  • Melay FSM
  • Controller Development
  • Sequence Detectors

Memory Modeling

  • RAM
  • ROM
  • LUT

Test Bench

  • Modeling a Test Bench
  • Test Bench for Combinational Circuits
  • Test Bench for Sequential Circuits
  • Test Bench for Memories Circuits
  • Test Bench for Controllers

Labs

  • Introduction to XILINX tools
  • Entering HDL code
  • Synthesis and implementation
  • Creating Test Bench
  • Simulation
  • Physical Realization

Project

UVM

MODULE1 :
- OOP Basics
- OOP applied to System Verilog
- Typical Verification Environment Example
- Verification phases
- Verification Challenges
- Why UVM ?
- How UVM addresses these verification challenges
- Introduction to UVM
- Examples using UVM reporting Mechanism

MODULE 2:
- Phases of UVM
- TLM Introduction
- PUSH / PULL Port in TLM
- Examples covering PUSH /PULL in UVM
- Analysis ports with Examples

MODULE 3 :
- UVM ,a structured Approach
- UVM Registry
- UVM Reporting Mechanism
- UVM Factory

MODULE 4:
- UVM Objects
- UVM components
- UVM Class hierarchy
- Example Environment creation using all the UVM components along
with Sequence Item Factory methods for UVM in SV as well as
UVM communication with SystemC

MODULE 5 :

- UVM Sequence
- UVM Sequencer
- UVM sequence phases
- Creating Request Response sequnce and sequencer in Push Pull Mode
- UVM macros like uvm_do ,uvm_do_pri_with …….
- Examples covering all the above topics

 

MODULE 6:
- Virtual Sequence

- Virtual Sequencer
- Sequencer Arbitration
- Disabling sequencer
- Examples covering all the above topics


MODULE 7:
- Object /component Type overriding using Factory
- Object /component Instance overriding using Factory
- Call backs in UVM
- DataBase structure in UVM i.e Resource and config DB
- Advanced UVM Examples like
: creating pipeline driver
: Using config DB in sequence /Sequence Item

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